Semiconductor device performance improvements have historically been achieved by reducing device dimensions. The device miniaturization trend has progressed to a point where contemporary ICs are fabricated with deep sub-micron device feature sizes. The trend has placed increased emphasis on miniaturization of discrete passive components that are required to function with miniaturized active devices.
In addition to reduced feature sizes, recent trends have focused on replacing conventional aluminum as the conductive medium with copper. As wire widths in integrated circuits continue to shrink, the electrical conductivity of the wiring material itself becomes increasingly important. In this regard, aluminum which has been the material of choice since the integrated circuit art began, is becoming less attractive than conductors such as gold, silver, and especially copper. Copper is also more resistant than aluminum to electromigration, a quality that grows in importance as wire widths decrease. Copper has found increased application in the creation of discrete components, most notably discrete inductors that are formed above the surface of a semiconductor-based IC. Copper provides advantages of improved conductivity and reliability but does provide a challenge where a layer of copper must be patterned and etched. The process challenge is due partially to the fact that copper does not readily form volatile species during the etching process. To overcome the etch problem, other methods of creating interconnect lines using copper have been proposed including depositing copper patterns using selective electrodes plating.
The speed limit of advanced ICs is set by the delay in signal propagation in conductive interconnect lines, which is determined by the time constant of the line. The time constant is the product of the resistance, R, of the line and the capacitance, C, between the line and all adjacent lines; hence, an RC time constant. Using a lower resistivity conductive material decreases interconnect RC time constant delays resulting in an overall increase in device speed.
Resistance, R, of a structure is determined by the following equation
  R  =            ρ      ⁢                          ⁢      L        WT  where ρ is the resistivity of a conductive material, L is the length of the conductive material, W is the width of the conductive material, and T is the thickness of the conductive material.
The limited availability of low-loss integrated inductor structures has long hindered the development of integrated circuits (IC) such as passive filters, voltage controlled oscillators (VCO), matching networks, and transformers. Contemporary portable communications environments strive to achieve more fully integrated circuits that operate at radio frequency (RF) and microwave frequencies. Recent trends indicate a push to integrate entire receivers onto a single substrate. Planar inductors tend to suffer from high losses and low quality factors (Q factors) at radio frequencies. The losses and low Q factors are generally attributable to dielectric losses incurred from parasitic capacitances and resistive losses due to the use of thin conductors with relatively high resistance. The Q factor is defined as
      Q    =                  E        s                    E        1              ,where Es is energy that is stored in the reactive portion of the component and El is energy that is lost in the reactive portion of the component. The Q value of an inductor can also be expressed with the equation
  Q  =                    ω        0            ⁢      L        R  where ω0 is the resonant frequency of oscillation of the inductor, L is the inductance value of the inductor and R is the resistance of the inductor. As the equation indicates, for a given value of ω0, the Q value of the inductor increases as the resistance of the inductor is decreased. As the resistance of the component approaches zero, the Q factor approaches infinity.
For high frequency signals, such as signals in the 10 GHz to 100 GHz range, the value of the Q factor obtained from silicon-based inductors is significantly degraded. For applications in this high frequency range, monolithic inductors have been researched using a base other than silicon for the creation of the inductors. Such monolithic inductor have, for instance, been created using sapphire or GaAs as a base. These inductors have a considerably lower parasitic capacitance than their silicon counterparts and therefore provide higher frequencies of resonance of an LC circuit. Where, however, more complex applications are required, the need still exists to create inductors using silicon as a substrate base.
With reference to FIG. 1, a cross-sectional view of a prior art copper line forms a portion of an integrated inductor. A substrate 101 having a passivation layer 103 is coated with a thin sputtered layer of metal 105, such as titanium-tungsten (TiW), thus forming a barrier layer and providing for adhesion of a subsequent sputtered layer of copper 107. A thick layer of photoresist 109 is then applied using, for example, spin-on techniques, over an uppermost surface of the sputtered copper layer 107. The photoresist 109 is exposed and the exposed portion is removed, leaving behind a trench within which to deposit electroplated copper 111.
The patterned photoresist serves as a mask during the copper electroplating process. During the electroplating step, the top of the substrate 101 and passivation layer 103 conducts plating current through the sputtered layer of metal 105 and sputtered layer of copper 107 beneath the photoresist 109 by connecting a cathode lead (not shown) to the substrate 101 along an edge of the substrate 101. Current flows along the cathode lead from the anode in a copper solution to the substrate 101, depositing a thick layer of electroplated copper 111 along the photoresist trench in the process. Plating times and photoresist thickness control deposited thickness and grain size for the resulting electroplated copper 111.
Once the electroplated copper 111 is deposited, a wet or dry (e.g., plasma) organic strip process is performed to remove the photoresist 109. An additional etch is performed to remove the sputtered metal layer 105 and sputtered copper layer 107 from the top of the passivation layer 103, electrically isolating the inductor. Connections to the ends of the inductor are made through via holes (not shown) in the passivation layer 103 allowing the sputtered and plated metal layers to contact metallization layers (not shown) within the IC.
However, process steps subsequent to electroplating leave rough edges and undercuts on sidewalls of inductors formed from copper. The sidewall roughening is especially deleterious in RF applications where RF performance of the copper inductor depends on the copper wall profile. Therefore, what is needed is a method for producing thick copper lines which may be formed into inductors having smooth and vertical sidewalls.